What are $past compared to on first clock event?

SystemVerilog
,
1

Hi,

I have an assertion which using $past to basically check whether the current value is same as previous value.
This is just a simple example:

property test(logic cur_st);
@(posedge clk)
disable iff (!rst )
( $past(cur_st,1) == cur_st );

Assume that the assertion is always true.
Here is the waveform condition:
@0 cur_st = X; clk = 0;
@5 cur_st = 0; clk = 0;
@10 cur_st = 0; clk = 1;
@15 cur_st = 0; clk = 0;
@20 cur_st = 0; clk = 1;

on the posedge clk, what does the $past check to? it suppose to check value of cur_st one previous clock earlier, right?

2

In reply to jesslyn993:

Value will be X (unknown) for all clocks less than start of simulation as referred to by $past. That’s why it is recommended to code it with a delay (equal to that of number of $past clocks). In your example, modify it as:


property test(logic cur_st);
@(posedge clk)
disable iff (!rst )
##1 
( $past(cur_st,1) == cur_st );

Obviously the above property isn’t going great deal of checking as it simply wants that signal to be stuck at a value throughout the simulation. But you already said it is just an example.

HTH
Srini
www.verifworks.com

3

In reply to Srini @ CVCblr.com:

Thanks Srini for the reply. Yes, the property is just a simple property which has not much meaning.

Your answer is valuable to me. It’s clear my doubt. Thanks for you help.