In reply to jesslyn993:
Value will be X (unknown) for all clocks less than start of simulation as referred to by $past. That’s why it is recommended to code it with a delay (equal to that of number of $past clocks). In your example, modify it as:
property test(logic cur_st);
@(posedge clk)
disable iff (!rst )
##1
( $past(cur_st,1) == cur_st );
Obviously the above property isn’t going great deal of checking as it simply wants that signal to be stuck at a value throughout the simulation. But you already said it is just an example.
HTH
Srini
www.verifworks.com