Wait statement in initial block is not hanging the simulation

SystemVerilog
,
1 
module testbench;
reg a = 0;
initial
begin
	#10;
	wait(a);
	$display("FINISH");
end
endmodule

The execution is ending after 10 ticks. I am expecting the code to hang.

2

In reply to prashantg:

An event-driven simulation ends as soon as there are no more events to execute. A wait() is not a looping statement.