Variable within SVA cover property

SystemVerilog
,
1

We know that below display statement gets executed when the property passes…


property TRY;
    @(posedge clk) a |-> b;
endproperty
COVER_TRY: cover property(TRY)$display("COVERED");

I want to avoid enabling coverage(during initial dev phase) and do a book-keeping using a variable.
My intention:


 if(cover property (TRY) passes)
     update the corresponding variable[index] = 1;
 else
     do-nothing

Something like the below one, just instead of $display**:**

  
COVER_TRY: cover property(TRY) , cov_info[0] = 1;

Above code is syntactically wrong,
however its just to illustrate my thoughts.

2

In reply to rshrig:

One can not access a non-local variable in cover property directly from the property itself. I use the following workaround. Basically use a function that increments the counter. Note that if there are multiple counters, you can make a generic function that increments depending on the input arguments:


  int my_var; // variable to be incremented
  property TRY;
    @(posedge clk) a |-> (b,my_func()); // when property passes, my_func is invoked
  endproperty
  COVER_TRY: cover property(TRY) $display("COVERED");
  
  // Increment the variable in some function
  function void my_func();
    my_var++;
  endfunction

There may be other workarounds as well but this is the one that is convenient if we have small number of variables to be manipulated.

3

In reply to sharvil111:

Hi Sharvil,
Thanks is it worked !