Using variable instead of hard coded bits

SystemVerilog
1

In below code i want to get value of my_data[startbit:endbit] and store in dt. i dont want to hardcode

  bit [31:0] my_data = 32'h23456789;
  bit [31:0] dt = 0; 
  int startbit = 31; //not constant 31 ..may change this is only example
  int endbit = 28;
  dt = my_data[startbit:endbit];   //dont want to hardcode this as my_data[31:28]
  $display("dt= %0h",dt1);

above code gave error.

So tried to replace the dt assign statement as below using $sformatf but didnt work.Can anybody help me how can i do this?
dt = $sformatf(“my_data[startbit:endbit]”);

2

In reply to anupshet09:

SystemVerilog does not allow part selects of a packed array to have a variable width. What most people do that is synthesizable is a shift and mask

dt = (my_data >> endbit) & (32'hFFFFFFFF << (startbit - endbit + 1))

You could also use a for-loop to assign bit-by-bit

for (ii=endbit,jj=0; ii<=startbit; ii++,jj++)
   dt[jj] = my_data[ii];
3

In reply to dave_59:

Thanks Dave.