I was trying an example related to .matched :: EDA_Matched
As Dave commented in an earlier thread :: property-vs-sequence-sensitivity-list
"Sequences generate an event upon upon reaching an endpoint "
At TIME : 75 both posedge of Busclk as well as Negedge of sysclk occurs .
RdS.matched is True at TIME : 75 and even Negedge of sysclk occurs at the Same time .
I have following questions ::
[Q1] Can I say there is a race condition between the sequence RdS generating an event ( on completion ) and @( negedge sysclk ) ?
SystemVerilog has event.triggered to avoid race conditions .
Is there a similar option for assertions too ?
[Q2] Does the LRM mention in which region does the RdS.matched occur ?
In reply to hisingh:
Section 16.13.6 Sequence methods in the IEEE 1800-2017 SystemVerilog LRM answers both your questions. Sequence methods are set in the observed region. There is no race with a clock edge which happens in the active region.
In reply to dave_59:
LRM 16.13.6 Sequence Methods ::
(1) It can only be used in sequence expressions. Unlike triggered, matched provides synchronization between two clocks by storing the result of the source sequence until the arrival of the first clock tick of the destination sequence after the match.
(2) The matched status of the sequence is set in the Observed region and persists until the Observed region following the arrival of the first clock tick of the destination sequence after the match.
Via (1) "until the arrival of the first clock tick of the destination sequence after the match. "
Via (2) “persists until the Observed region following the arrival of the first clock tick of the destination sequence after the match.”
So RdS.matched is True from Observed Region of TIME:75 to Observed Region of the 1st clock tick of destination sequence i.e TIME : 85
Hence at TIME : 85 when the 1st clock tick of the destination sequence occurs ,the antecedent is True .
I have a question about using :: wait( seq.triggered )
wait statement executes in active region whereas triggered status of the sequence is set in Observed Region .
In System Verilog Event Region I observe a feedback path from Observed region to Active region .
Can I say wait( seq.triggered ) is an example for the feedback path ?