Usage of local parameter in a class

SystemVerilog
,
1

hi:

I saw a piece of code in the IEEE Standard for SystemVerilog (8.25.1), which is inconsistent with my test results.
My test here: Edit code - EDA Playground , same as the first example of Standard 8.25.1.
The inconsistency is that the standard says that the code in line 17 is illegal, but the measured result is OK

So, what is the reason?

thanks

2

In reply to jianfeng.he:

I appears that some tools are allowing this. It is the same as if you had wrote

bit arr[C#()::q] = '{default:1'b1};