Understanding triggering cover groups using .sample()

SystemVerilog
, , , ,
1

Hello

I am looking at some code as below (only psedo code posted.) and curious how .sample() works for triggering cover group.


covergroup A
option.per_instance=1; 
//some code here. bins etc
endgroup

covergroup B
// some code here. bins etc
endgroup

For each covergroup I have multiple instances


A a_instA, b_instA;
B a_instB;

In body task I am triggering with .sample.


do begin
 a_instB.sample();
`uvm_do(xyz);
 coverage = some_task_call();
end
while (coverage !=1)

However I see that coverage is measured by combined coverage of a_instA, b_instA and a_instB. (a_instA.get_inst_coverage ==100 && b_instA.get_inst_coverage ==100 && a_instB.get_inst_coverage == 100). Test is also printing these coverage values with each iteration and I see them increasing for each cover groups instance. My understanding was that whatever instance calls .sample() only that instance coverage is measures after trigger. I am surprised to see other coverage increasing as well.

2

In reply to aashishs2603:

Calling sample() on a covergroup instance can only increase coverage of that instance. You will have to show how you are display the computed coverage.

3

In reply to dave_59:

Thanks Dave
wanted to double check my concept.
I actually rewrote the code sample so that I can share here but found that only coverage called by sample is increasing like you said. I would debug legacy code and check why and how others were getting updated.

Thanks
Aashish