Time variable rounding

SystemVerilog
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1

Hello everyone,
I wrote code which includes time variables,
but when i displayed this variable, it has been rounding a higher number.
how do i prevent that?

Thanks for your answers.

class …;

const realtime tclk_half = 31250ps;
///////////////////////////////////////////////
build_phase;
$timeformat(-12,0,“ps”,8);
///////////////////////////////////////////////
run_phase;
`uvm_info(get_type_name(),$sformat(“time : %t”,tclk_half), UVM_LOW)

Output :
time : 31300ps

2

In reply to nrllhclb:

Check timescale value. Precision should be ps.


`timescale 1ns/1ps
3

In reply to Rahulkumar:

thank you for the answer, it works.