T flipflop clock cannot be seen in simulation graph

SystemVerilog
, ,
1

Hi, I tried to simulate T flipflop in vivado. But for some reason the square wave (clk) pin is not working. if some one can point where I am going wrong it would help me a lot.
here is my simple code.
test bench:


module tb;
reg t; 
reg clk;
reg rst; 
wire q;

tff dut(.t(t),
.clk(clk), 
.rst(rst), 
.q(q));
 
always #5 clk = ~clk; 
 
 initial begin 
 t=0;
 rst=0;
 #10
 t=1;
 rst=1;
#20 $finish;
 end

endmodule

design file

`timescale 1ns / 1ps
module tff(
    input t,
    input clk,
    input rst,
    output reg q
    );
    
always @ (posedge clk) begin
if(!rst)
q<=0;
else
if(t)
q <= ~q; 
else
q <= q; 
end
endmodule

graph:

2

In reply to Ashokraj:
You have declared the clock as reg which is a 4 state data type having default value x. So either initialize it or use 2 state data type to declare clk.

3

In reply to bdreku:

I have implemented d flipflop, some other digital circuits using the similar declaration of clk. can you tell me how can I declare the two state data type or intialization of it.

What all I know is, declaring it as a reg clk only !

4

In reply to Ashokraj:
Either declare the clk as bit or add following line in your tb module to initialize it: initial clk=0;

5

module tb;
reg t;
reg clk;
reg rst;
wire q;

tff dut(.t(t),
.clk(clk),
.rst(rst),
.q(q));

initial begin
clk=0;
end

always #5 clk = ~clk;

initial begin
t=0;
rst=0;
#10
t=1;
rst=1;
#20 $finish;
end

endmodule