SystemVerilog Coverage Point Percentage is incorrect

SystemVerilog
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For example I drive 3 test vectors of 4 bits width. the coverage should be 3/16 which is correct. But When the width of the vector gets larger than 6 bit, the tool starts giving incorrect coverage percentage. Any advice?

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In reply to Jaafar Hassan:

My advice is to explain what you mean by “incorrect” and show some code.