System verilog

SystemVerilog
1

module ttttttt;
class parent;
function void tt;

   virtual function ttt;
    $display("i m the parent");
  endfunction
endfunction

endclass

class child extends parent;
function ttt;
$display(“i m the child”);
endfunction
endclass

parent p1;
child c1;
initial
begin
p1=new;
c1=new;
p1.tt;
c1.tt;
p1=c1;
p1.tt;
end
endmodule

i am getting error

2

In reply to nalla raghu:

It would help if you

  • Learned how to ask a question better. You have no question here.
  • Used code tags in your posts to make them more readable
  • Explained the results you are expecting versus what you saw instead.

You endfunction does not line up.