Syntax error: token is #

SystemVerilog
,
1

Hi,

The following code of a file gives syntax error in VCS for

typedef

line. The message displayed is:

Error-[SE] Syntax error
Following verilog source has syntax error : FILENAME, LINENUMBER : token is #
typedef basic_reset_seq
#(qrst_pkg::POLARITY_ACTIVE_HIGH,qrst_pkg::MODE_ASYNC_TO_CLK,qrst_pkg::MODE_SYNC_TO_CLK)
dut_basic_reset_seq ;

`ifndef tb_base_test__SV
`define tb_base_test__SV
`include "uvm_macros.svh"

import uvm_pkg::*;
import qrst_pkg::*;
typedef basic_reset_seq #(qrst_pkg::POLARITY_ACTIVE_HIGH,qrst_pkg::MODE_ASYNC_TO_CLK,qrst_pkg::MODE_SYNC_TO_CLK) dut_basic_reset_seq ;
class tb_base_test extends uvm_test;

`uvm_component_utils(tb_base_test)
 dut_basic_reset_seq some_reset;
//Some code
//Some extern functions/tasks
endclass : tb_base_test

//extern functions/tasks definitions
`endif

Can anyone please help me on this. Thanks.

UPDATE: I tried removing the tyepdef and using the parameterized class name directly while declaring the handle inside class. Still no luck.

2

I got this resolved, but posting the solution if it would help someone later. The issue was because compiler was not able to see

basic_reset_seq

because it was included in some other package which was not imported. But the error message seems so vague and misleading when it complains about # character. Keeps you thinking about the nuances of parameterized class when the problem is something different.

3

In reply to rishikpillai90:

Whenever you get a syntax error, it is usually a problem with the token before where the error message points to.

4

In reply to dave_59:
Thanks Dave for the information. This shall be useful in future.