Is Super.new() in derived class constructor optional?

SystemVerilog
,
1

Hi All,

I got a unexpected (maybe to me it is strange) result from the fallowing code

class base;

  function new();
    $display("PARENT CLASS CONSTRUCTOR\n");
  endfunction
endclass

class child extends base;
  function new();
    $display("CHILD CLASS CONSTRUCTOR");
  endfunction
endclass

initial begin
child c;
c= new();
end

/***RESULT/
PARENT CLASS CONSTRUCTOR
CHILD CLASS CONSTRUCTOR

Is super.new in derived class is optional !!!
then why we write super.new() always in derived class constructor, is there any advantage of doing so ?

thanks in advance

2

From SV 1800-2012 LRM:

A super.new call shall be the first statement executed in the constructor. This is because the superclass shall be initialized before the current class and, if the user code does not provide an initialization, the compiler shall insert a call to super.new automatically.

3

Please use code tags to make you code more readable. I have added them for you.
The LRM says:

A super.new call shall be the first statement executed in the constructor. This is because the superclass shall be initialized before the current class and, if the user code does not provide an initialization, the compiler shall insert a call to super.new automatically.

Normally you need to explicitly call super.new(…) to deal with required construct arguments. The one that is implicitly inserted has no arguments. Even if you have no constructor arguments, it is always a good idea to explicitly call super.new() to make your code more readable.

4

In reply to Sushrut Veerapur:

thanks sushrut

5

In reply to dave_59:

thanks dave,
i tried to find for the code tags , But i did not any link . please provide the link to know about the code tags.

6

Dave, I think we should call super.new(), when there is an arguments in the new function !! if we are newing with out any arguments we can avoid super.new()
-sivajsyamm

7

In reply to shivabachu:

Look at the right-most button above the dialog box where you type your message. OR read Please format your code with [code] and [/code] tags or [systemverilog] and [/systemverilog] | Verification Academy

8

In reply to sivasyammj:

SystemVerilog is full of default implicit rules that are very hard to remember, as indicated by the original question. Most of the time you are going to need to call super.new with arguments anyways. If you use a methodology like UVM, you will wind up calling it nearly 100% of the time.

I think it is just easier to remember calling super.new 100% of the time.