Struct Keyword

SystemVerilog
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1

Hello all,

Can you please tell me the exact difference of formal & informal grouping in data organisation while using struct keyword?
Is struct keyword exists in Verilog?
If it exists?How it is different from verilog?

Thanks in advance!

2

In reply to SANJAIKUMAR:

Can you explain the context where you read about “formal & informal grouping”?

The struct datatype exists in SystemVerilog, not in Verilog.

3

In reply to dave_59:

Hi Dave,
Thanks for your reply.
what i really meant about formal & informal grouping?
for example:
struct { bit[7:0] a,int b} struct_name;

Here, collection of items of different data types useful for data organisation based on formal grouping whereas in verilog it is ordered in informal way of grouping.

Thanks in advance.