Stability with respect to another signal

SystemVerilog
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1

Hi

I want to check that Signal A should not toggle until Signal B is 1. I have coded various options but they are either failing at 0 time or when A and B both are toggling at the same time.

Please help.

2

In reply to pRoSpEr:

One of the many tries:

property check;
@(A) ((A !== 1’bx) |->##0(B === 1));
endproperty

3

In reply to pRoSpEr:

Can anyone provide a solution please?

4

Signal A should not toggle until Signal B is 1. I have coded various options but they are either failing at 0 time or when A and B both are toggling at the same time.
@(A) ((A !== 1’bx) |->##0(B === 1));

Are A and B synchronous to a clock?
What do you mean by toggle? A change?
Maybe those assertions would work:


ap_b0: assert property(@(posedge clk) ##1 B==0 |-> $stable(A)); // no change if B==0
ap_b1: assert property(@(posedge clk) ##1 B==1 |-> strong(##[1:$] $changed(A))); 
   // A will hanged sometime in the future. 
May want to use **##1 $rose(B==1)** instead 
ap_b_rose: assert property(@(posedge clk) ##1 $tose(B)==1 |->  $stable(A));

Note |-> ##0 x is SAME as |-> x

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
5

In reply to pRoSpEr:

Unless I am missing something, here is a simple solution:


  // Assuming default clocking
 b_shall_be_1_when_A_changes : assert property 
  (##1 ! ($stable(A)) |-> B);

Does that help? If not, do provide a failing trace, we can assist further.

Regards
Srini
http://www.verifworks.com

6

In reply to Srini @ CVCblr.com:

Hi Srini,

Thanks for the solution.

7

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks for the solution.