Signal A should not toggle until Signal B is 1. I have coded various options but they are either failing at 0 time or when A and B both are toggling at the same time.
@(A) ((A !== 1’bx) |->##0(B === 1));
Are A and B synchronous to a clock?
What do you mean by toggle? A change?
Maybe those assertions would work:
ap_b0: assert property(@(posedge clk) ##1 B==0 |-> $stable(A)); // no change if B==0
ap_b1: assert property(@(posedge clk) ##1 B==1 |-> strong(##[1:$] $changed(A)));
// A will hanged sometime in the future.
May want to use **##1 $rose(B==1)** instead
ap_b_rose: assert property(@(posedge clk) ##1 $tose(B)==1 |-> $stable(A));
Note |-> ##0 x is SAME as |-> x
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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