Hi
I want to check that Signal A should not toggle until Signal B is 1. I have coded various options but they are either failing at 0 time or when A and B both are toggling at the same time.
Please help.
Hi
I want to check that Signal A should not toggle until Signal B is 1. I have coded various options but they are either failing at 0 time or when A and B both are toggling at the same time.
Please help.
In reply to pRoSpEr:
One of the many tries:
property check;
@(A) ((A !== 1’bx) |->##0(B === 1));
endproperty
Signal A should not toggle until Signal B is 1. I have coded various options but they are either failing at 0 time or when A and B both are toggling at the same time.
@(A) ((A !== 1’bx) |->##0(B === 1));
Are A and B synchronous to a clock?
What do you mean by toggle? A change?
Maybe those assertions would work:
ap_b0: assert property(@(posedge clk) ##1 B==0 |-> $stable(A)); // no change if B==0
ap_b1: assert property(@(posedge clk) ##1 B==1 |-> strong(##[1:$] $changed(A)));
// A will hanged sometime in the future.
May want to use **##1 $rose(B==1)** instead
ap_b_rose: assert property(@(posedge clk) ##1 $tose(B)==1 |-> $stable(A));
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
In reply to pRoSpEr:
Unless I am missing something, here is a simple solution:
// Assuming default clocking
b_shall_be_1_when_A_changes : assert property
(##1 ! ($stable(A)) |-> B);
Does that help? If not, do provide a failing trace, we can assist further.
Regards
Srini
http://www.verifworks.com