Shift operator

SystemVerilog
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1

Dear Community,

Can someone please explain following lines of code:

readdata = (('hFE0>>2) << 4) | (REG_OP_CFGWR << 0);
regData = EXT_CTRL << 4 | REG_OP_CFGWR;

It generates same data to write inside PCIE registers

2

In reply to haykp:

Without seeing the declarations of all operands, it’s impossible to tell you exactly what is being performed. The first statement has a few superfluous operations. I’m guessing it was automatically generated, or cut&paste from similar expressions.

3

In reply to dave_59:

Dear Dave,

Thanks for looking on this.
This is little differnet example, but same operations:

reg   [31:0] 	  regData;

typedef enum {
    CFG_NONE = 32'h400, // CFG (AVIP & VIP) 
    VENDOR_ID = 32'h401, // Vendor ID (AVIP & VIP) 
    DEVICE_ID = 32'h402, // Device
    COMMAND=32'h4023
} regNumT 

regNumT type0reg[3:0];

typedef enum {
  OP_UNDEFINED = 0,
  OP_RESIZE = 1,
  OP_CFGWR = 3,
} OpT; 

regData = (type0reg[i] << 4) | (OP_CFGWR << 0);
regData = (COMMAND >> 2) | (OP_CFGWR << 0);
4

In reply to haykp:

Shifting a value left by 0 places has absolutely no effect on the value or its type. Maybe the person that wrote this was being paid by the size of the file.

5

In reply to dave_59:

Haha, thanks
I think this is automatically generated code. For some cases the shifting value is 0, other cases more than 0.
This is mechanism to write data into registers.