Shift operator

SystemVerilog
,
3

In reply to dave_59:

Dear Dave,

Thanks for looking on this.
This is little differnet example, but same operations:

reg   [31:0] 	  regData;

typedef enum {
    CFG_NONE = 32'h400, // CFG (AVIP & VIP) 
    VENDOR_ID = 32'h401, // Vendor ID (AVIP & VIP) 
    DEVICE_ID = 32'h402, // Device
    COMMAND=32'h4023
} regNumT 

regNumT type0reg[3:0];

typedef enum {
  OP_UNDEFINED = 0,
  OP_RESIZE = 1,
  OP_CFGWR = 3,
} OpT; 

regData = (type0reg[i] << 4) | (OP_CFGWR << 0);
regData = (COMMAND >> 2) | (OP_CFGWR << 0);