Related to Testbench top

SystemVerilog
,
1

Hi,

We will be creating testbench top component as module.

we will have instance of TB and DUT inside it,Generating clock.

My understanding is that we want to keep top as static member.Why?

Thanks
Bharath

2

SystemVerilog requires that all threads get started from the initial or always block of a module. Clocks are for the operation of the DUT, not the testbench. Since the clock is usually the most active part of your simulation, you will want to keep the levels of indirect assignments to a minimum. So have the code that oscillates the clock make direct assignments to the clock signal of your DUT.

Also, you do not always need a single top level module. See
https://verificationacademy.com/cookbook/emulation/separatetoplevels