Related to Handshake signals

SystemVerilog
1

I am having Producer with valid signal and consumer with ready signal.

my producer is generating data as fast as possible, and consumer sinking data at half rate.

without using any registers(like FIFO…) in between producer and consumer, how to avoid data loss

suggest some logic how to do.

if it is in verilog, it will help to me

Thank you,
Lakshman

2

In reply to Lakshman4178:
Without a FIFO or a HOLD or READY signal from the consumer, you get something like
I Love Lucy - The Chocolate Factory

Obviously, the producer needs to abide by the protocol, i.e., not producing data until consumer is ready. When you say suggest some logic how to do, it’s really up to the consumer to generate a READY or HOLD signal at it’s interface when it is ready to accept data. That information is within the logic of the consumer.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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