Regarding assertion

SystemVerilog
1

Hi,
The assertion in the above is failing , I wanted to write an assertion , that at the negative level of sclk the data_in === dout and at the positive level of the sclk the data_in should latch , i.e. previous data should come .
So I have implemented two assertions separate , but in waveforms the data is correct but the assertions are failing.

property ilatch;
   @(negedge sclk) disable_iff (!por_n || !gsrn)
      (mc1_inclk_en_a ) |-> (data_in === data_out);
endproperty 
INPUT_LATCH : assert property (ilatch)

property olatch;
   @(posedge sclk) disable_iff (!por_n || !gsrn)
      (mc1_inclk_en_a ) |-> ($stable(data_in));
endproperty 
OUTPUT_LATCH : assert property (olatch)
2

In reply to bijal:
See my reply on various SV evaluation regions. Sampling point of Assertions | Verification Academy


// "at the negative level of sclk the data_in === dout"
@(negedge sclk) disable_iff (!por_n || !gsrn)
      (mc1_inclk_en_a ) |-> (data_in === data_out);
// [Ben] This says that @(negedge sclk) with a matched antecedent the sampled values 
// of both data_in and data_out are equal.  This sampling is in the Preponed region, 
// which is the current time slot before any net or variable has changed state.
//----------------------------------------
// "...the positive level of the sclk the data_in should latch , 
//  i.e. previous data should come"
@(posedge sclk) disable_iff (!por_n || !gsrn)
      (mc1_inclk_en_a ) |-> ($stable(data_in));
//[Ben] This says that @(posedge sclk) with a matched antecedent the sampled value of data_in
// has not changed and is equal to the value of data_in sampled in the previous @(posedge sclk.
// If you want "previous data"
@(posedge sclk) disable_iff (!por_n || !gsrn)
      (mc1_inclk_en_a ) |-> ($past(data_in));
// This says that @(posedge sclk) with a matched antecedent the sampled value of data_in
// can change and is equal to the previously sampled of data_in sampled 
// in the previous @(posedge sclk. Thus data_in could be =5 now and 20 in the previous sample. 
// If this is the the very first clock, then that previous value is its initialized value.

I don’t understand why you have those two requirements. If logic is activated at the posedge of the clock, then use this for all your assertions. If you are concerned about setup, do something else, possibly 1800’2017 31.3 Timing checks using a stability window

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
  3. Papers: