RANDC and RAND variables in the same class: the second one should constraint the first one

SystemVerilog
1

Hi.

I have two random members in the same class. The “first” one is random and the result of
its randomization should be the constraint for the randomization of the other, randc.

For istance:

randc A (0,1,2,3,4,5,6,7,8,9)
rand B (3,5,7)

if B.randomize = 5 then the randomization of A should return all value less than B.

Is it possible to do it in the same randomization?

Thanks.

2

In reply to pasciuto:
Withing the same scope if rand A and randc B gets randmoze then simulator always randomzie the all randc variable before rand variables. In addition, you can not use the solve before on randc variable. In your requirement constraint solver will fail when it tries to solve the constraint. you should review again your requirement. Havind said that you can randomize in post_randomze method by using in line constraing method.


function void post_randomize();
   std::randomize(B,A) with {B < A};
endfunction
3

In reply to pasciuto:
You can do

randc int A;
rand int B;
constraint c {
 A inside {[0:9]};
 B inside {3,5,9};
 B==5 -> A<5;
}

Realize that implication x → y is no different from a regular boolean expression
(!x || y). So there is no variable ordering involved (nor is it allowed with a randc variable as kddholak mentions)

4

I guess it’s a replication of this post link …

5

In reply to alexkidd84:

Indeed