Races between input clk and internal combinational logic?

SystemVerilog
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1

I learn from the book entitled ,SVA: The Power of Assertions in SystemVerilog Second Edition’’ by E. Cerny, S. Dudani, J. Havlicek and D. Korchemny.

There is the following exercise 3.1:
Identify all potential cases of glitches and races in the following code. Assume that clk changes at most once per time step.

I wonder if it possible that race happens between input clk and internal combinational logic?
If yes, then I would like to ask you how you work with SystemVerilog if it can be non-deterministic with such simple module?

I am pretty sure I have correctly identified potential glitches.

By the way, maybe some of you also have gone through that book and you know where I can find the solutions for the exercises?

2

In reply to mkru:

Mixing up blocking and non-blocking assignments within an always_comb is not good coding practice.

  always_comb begin
    v = in;
    not_v <= !in;
    v_or_not_v = v || not_v; // <- potential glitch
  end
3

In reply to kernalmode1:

Sorry, that’s just a typo, I have fixed this. Still the question is about glitches and races :).