Question regarding Blocking and Non Blocking assignments

SystemVerilog
,
1

Hi,

What will be the o/p of below code? I thought the O/P can be either a=b=0 or a=b=1 but when I simulated it on edaplayground I only see a=b=1

always @(posedge clk) begin
    fork 
    a = b;
    b = a;
      join
end
initial $monitor("a=%b, b=%b", a,b);
  end

Thanks

2

In reply to sj1992:

What is the initial value of a and b?
If that value is unchanged and same, then there may chance that it will give you 1 as output.

3

In reply to sj1992:

Please provide a complete example that demonstrates your question. There are so many variables regarding the code you posted (initial values, any other assignments, etc) that it is impossible to answer your question.

4

In reply to cgales:

This is the exact code and it is an sv file.

module test;

  reg clk;
  reg reset;

  reg a;
  reg b;

          
  initial begin
	a= 0;b=1;
    clk = 0;
    reset = 1;
    forever #5 clk = ~clk;
    
    
  end
  
  initial $monitor("a=%b, b=%b",a,b);
  
  always @(posedge clk) begin
    fork 
    a = b;
    b = a;
      join
  end
  

endmodule
5

In reply to sj1992:

There is a race condition between the fork/join statements. There is no defined order of execution of the forked statements, so you may see a variation in behavior between simulators. However, running repeatedly on the same simulator will give you the same results. Hence the reason you only see ‘a=b=1’.

Try reordering the statements in the fork/join block and see what happens.

6

In reply to sj1992:

A fork/join with no blocking delays executes exactly like a begin/end block, except the execution order of the statements inside is undefined.