In reply to cgales:
This is the exact code and it is an sv file.
module test;
reg clk;
reg reset;
reg a;
reg b;
initial begin
a= 0;b=1;
clk = 0;
reset = 1;
forever #5 clk = ~clk;
end
initial $monitor("a=%b, b=%b",a,b);
always @(posedge clk) begin
fork
a = b;
b = a;
join
end
endmodule