a question about the blocking assignment's scheduling semantcs

Question

hi，today i got a question about the blocking assignment,in the below 2 statements ,why is the blocking assignment scheduled the different region?
The first statement:

module xxx;
bit[7:0]    data_test;
.....
    initial begin
        data_test = #0 1;//i think that assign at inactive region; 
    end
    initial begin
        data_test = 2;//i think that assign at active region;
    end
 
    initial begin
        $display（"result",$sformatf("data_test is %0d",data_test)）;
    end
endmodule

the result is 1;which i think is all right;but the second statement
The second statement:

module xxx;
bit[7:0]    data_test;
.....
    initial begin
        data_test = #0 1;//To assign at inactive region;
        data_test = 2;//To assign at active region;
    end
    initial begin
        $display（"result",$sformatf("data_test is %0d",data_test)）;
    end
endmodule

in the statement the result is 2? how could it be?

Answer 1

Solution

dave_59

Forum Moderator

8281 posts

October 19, 2020 at 10:51 pm

In reply to yongci:
A blocking assignment always makes it assignment in the active region.

data_test = #0 1;

is the same as

temp = 1;
#0;
data_test = temp;

There are no good reasons to ever use a blocking assignment with an intra-assignment delay. They were part of the initial version of Verilog and no longer needed after non-blocking assignments were added.

The result of the first example could be 0 (the default value), or 2. There is a race condition between the second and third initial blocks.

The result of the second example is 0. I get this results on all the simulators I try.

- Dave Rich

Answer 2

yongci

Full Access

6 posts

October 19, 2020 at 11:38 pm

In reply to dave_59:

thks for dave's answering my question;
when i got the message that "There are no good reasons to ever use a blocking assignment with an intra-assignment delay.",i got the answer.in fact,in my daily jobs there is no usage of blocking assignment with an intra-assignment delay but recently i reread the systemverilog and do the test by myself.so here comes the problem;

the first example: i got what u say;

the second example:
before read your answer,the point that i ignored is that:the blocking assfinment after inter-assignment delay also pushed to the inactive region;
that is statement:
1.
initial begin
data_test = #0 1;
data_test = 2;
end
is the same as:
coding that now my understanding;
initial begin
tmp = 1;
#0;
data_test = 1;
data_test = 2;
end
coding that my ealier-understanding before read your message;
initial begin
fork
begin
tmp = 1;
#0;
data_test = 1;
end
data_test = 2;
join
end

Answer 3

yongci

Full Access

6 posts

October 19, 2020 at 11:46 pm

In reply to yongci:

the above coding has some error:
my coding and my result that write in the case doesn't match;because i code the wrong display;
the correct coding is changing the initial begin-end process about the $display-process;
that is :
change the initial begin-end in the two case:
initial begin
$display(xxxx);
end

into:
initial begin
#1;
#display(xxxx);
end

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