In reply to yongci:
A blocking assignment always makes it assignment in the active region.
data_test = #0 1;
is the same as
temp = 1;
#0;
data_test = temp;
There are no good reasons to ever use a blocking assignment with an intra-assignment delay. They were part of the initial version of Verilog and no longer needed after non-blocking assignments were added.
The result of the first example could be 0 (the default value), or 2. There is a race condition between the second and third
initial blocks.
The result of the second example is 0. I get this results on all the simulators I try.