Property specification using a generate block

SystemVerilog
, ,
1 

property is_x; 
  @ (clk) disable iff (rst_n !== 1) 
    ($isunknown(data) == 0);
endproperty: is_x 
 
assert property (is_x) else `uvm_fatal ("", "data is unknown")

Question:
If data goes from 1 bit to 16 bits (data[15:0]), how do I use a generate statement to rewrite the property/assertion shown above to keep the code concise?

Thank You!

2

In reply to new_to_uvm:

The built-in $isunknown can handle bit-vector and hence the code you’ve would work for 16 bits without any change.

Srini
www.go2uvm.org

3

In reply to Srini @ CVCblr.com:

Thank You Srini!