OOPS - assigning base class

SystemVerilog
,
1

As per OOPS, you can assign a derived class object to handle of base class type.
This is because derived class has all that is present in the base class.

Let us take the following scenario:
we have a base class. This has a variable (say var1 of) with access type local
A derived class is created from the base class
A top module creates handle of base class type
An instance of derived class is created
it is assigned to base class handle

Now, if I try to access the local variable, it would fail even though object assignment is legal. I understand that as the variable var1 is made local, it is not accessible to the derived class but the statement that is frequently used in OOPS that the derived class has all the properties of the base class and hence it is safe to assign a derived class object to base class handle does not look completely correct.

2

In reply to shatrish:

You can not access local variable in derived class. Local variable cannot be inherited in derive class.In spite of local variable you can use “protected” key word. And again you can only access the variable through methods which are described inside the class. You can not access the variable using “.” operator.
see encapsulation in verificationguide …

3

In reply to Subhra Bera:

I understand the access control of class variables in terms of local, protected and public.
Actually, my question was a bit different. This is in terms of allowing class variables assignation between base and derived classes.

It is legal to assign an object of derived class to a base class variable. The reason normally given is that all that is there in the base class is also in the derived class.

You can see the following examples where using real world examples, they explain this but do not mention that there are cases where it is fatal to assign derived class object to base class variable.

https://www.quora.com/Why-can-a-base-class-reference-variable-refer-to-a-derived-class-object-in-Java
http://www.learncpp.com/cpp-tutorial/121-pointers-and-references-to-the-base-class-of-derived-objects/

4

In reply to shatrish:

It is always legal to assign the handle of a derived class object to a base class variable. It would help to use consistent class terminology. Your use of local variable is out of context from what it means in SystemVerilog.

It would also help to show your original scenario in terms of code written in SystemVerilog.

5

In reply to dave_59:

In reply to shatrish:
It is always legal to assign the handle of a derived class object to a base class variable. It would help to use consistent class terminology. Your use of local variable is out of context from what it means in SystemVerilog.
It would also help to show your original scenario in terms of code written in SystemVerilog.

I am sorry about the loose terms I used.
I have edited my original post. I don’t have any example code as I am trying to get the concepts correct.

6

In reply to shatrish:

It seems you do not understand access control of class variables. And if you cannot create code snippets for the initial descriptions you wrote, then you need to study more.

we have a base class. This has a variable (say var1 of) with access type local

class base;
  local bit var1;
  bit var2;
endclass

A derived class is created from the base class

class derived extends base;
  bit var3;
  function void method;
    // this method can access var2 and var3, but not var1
  endfunction  
endclass

A top module creates handle of base class type

You meant to say “A top module creates a variable (base_h) of base class type”

An instance of derived class is created
it is assigned to base class handle

module top;
  base base_h;
  derived derived_h;
  initial begin
    derived_h = new;
    base_h = derived_h; // this is always legal
    base_h.var2 = 1; // can only access var2
    derived_h.var3 = 1; // can access bot var2 and var3
  end
endmodule