Non-overridable parameter

SystemVerilog
,
1

Is it possible to somehow declare a module parameter as constant so that it cannot be overriden by any top module which instantiates the module.

parity_checker #(
   parameter DW = 32     // This parameter has to be constant in the module, cannot be a configurable one,
)
(
   input  logic [DW-1:0]   din,
   output logic [DW/8-1:0] parity
);

The idea is I just want to use DW everywhere in the code for readability and deriving some other parameters, including while declaring port size. And I don’t want top modules or Testbenches to override this parameter as a configurable parameter because the hardware inside is tailored only for 32-bit implementation. If it happens so, it should throw a compilation error or so. Is this possible in SV? Is macros the only way to get around this?

2

In reply to Mitu Raj:

Verilog has the provision to define non-configurable module constants using localparam

 localparam DW = 32 ;
3

Didn’t know localparam could be used for port dimensions. Vivado gave me error as unidentified identifier on port dimension when localparam was declared inside module. But it was fixed when localparam was declared at top like:

parity_checker #(
   localparam DW = 32    
)
(
   input  logic [DW-1:0]   din,
   output logic [DW/8-1:0] parity
);

Thanks…

4

The following solution works ::


module  parity_checker (   din , parity ) ; 
  
   localparam DW = 32 ;    

   input  logic [DW-1:0]   din ; 
  output logic [DW/8-1:0] parity ;
5

In reply to ABD_91:

Verilog-2001 style ports are recommended. Each port declared once.