Need help in writing assertion

SystemVerilog
,
1

Hi All,

I have come across one scenario, Need to implement assertion for that.

pseudo code is like::

always@(posedge clk) begin
                          if( there is change in ip) begin
                                ip1 = ip;
                              @(negedge clk)
                                if(op == !ip1)   //here ip1 value is ip value at posedge of the clock. 
                                 $display("assertion pass");
                                else
                                 $display("assertion fails");

Here input sampled at posedge, output is negation of input, i want to check at next negedge output is negated of posedge input.when ever there is change input i need to trigger this assertion.

How to write assertion for this.

Thanks,
Hanumanth.

2

In reply to Hanumanth92:

property p;
  bit ip1;
  @(posedge clk) $changed(ip),ip1=ip |-> @(negedge clk) op = !ip1;
endproperty

assert property (p) $info("assertion pass"); else $error("property fails");

There’s no need for saving ip in a local variable ip1 if it’s not going to change on the negedge.