Mapping of inputs & ouputs

SystemVerilog
,
1

hi,

I needed to map input and output for these 4 conditions.
1.one input to one output.
2.many inputs to one output.
3.many inputs to many ouputs.
4.single output to many inputs.

I am not able to figure out ,how exactly i need to approcah for this type of condition.Mapping of one input to one output is what i was doing till now.This type of prob, i havent came across till now.
Can anyone please help me with this ?

ps-for simplicity, in my system if iam having 4 inputs and 4 ouputs with a size of [2:0]each,along with multiple clocks.

2

In reply to veeresh_03:

  1. Many inputs to one output → multiplexer with a select signal that determines which input gets routed to the output.

  2. Many inputs to many outputs → combination of multiplexer and demultiplexer.

  3. Do you mean single input to many outputs? That would be a demultiplexer with a select signal, or just directly tying the single input to all the outputs.

3

In reply to sbellock:

hi,

Thank you sbellock for your reply.
but i have got the condition to model (many inputs to single output) using arbiter with a round robin & fixed priority,for rest mapping i have not got compulsion.
As far as i know,i will be having two signals(reuest & grant) and 1 clock for arbiter.I am not able to know how to keep the select condition for using arbiter.

below is my pseudo code…

module xyx;
inputs [n];
ouputs [n];
input clk;


logic condition[1:0];

parameter condition1=2'b00,cond2=2'b01,cond3=2'b10,cond4=2'b11;

always@(posedge clk)
begin
case(condition)
cond1:  //one to one mapping
        output1=input1;
        output2=input 2;

cond2: //arbiter 

cond3: //comb of mux & demux

cond4: //dmux with select sig

default:

endcase

end
endmodule

ps:Can you tell me ,if this is the right approach ? and also how about arbiters.how do i need to code them for rr with fixed priority.Can you please elaborate me on this along with the code for arbiters ?

Regards,
shubham

4

Can you tell me ,if this is the right approach?

I have no idea, as your specification is a bit vague. But it sounds like you need to read up on round robin arbiters and learn how they work before you attempt to code one up.

This looks like a good place to get started.

5

In reply to sbellock:

hi sbellock,

Thanks for the lead.
May be i havent specified you clearly,thats why it might be looking vague.
ok,I will go through the arbiter documentation.

6

In reply to sbellock:

hey sbellock,

I have gone thorugh a bit of documentation and found it really helfpul.
Thanks again.

Now the new problem arises regarding how to combine them.
My scenario is as follows.
Presntly i have made 3 modules,mod1(buffer),mod2(arbiter),mod3(mx2dx).I have created a top module and instantiated all of them inside it by using same signal names.

ok, after instantiation i have got 3 instances dut_buf,dut_arb,dut_mx2dmx.

if iam using case statement[1:0] then i will write 3 cases, 4th case and defaul ,assume as 0.

Currently iam using instance handle to insert the values in my top module for inputs and output for different cases to check the approach.

Though the code is compiling error free, i dont think this is the right way.Even if its right way,how should i write a testbench for it ?

can you give me any example where i am using 3 modules and clubbing them inside one top module with the same set of signals and intsantiating them and how to verify the working?

It would be really helpful,if u can guide me through this.

Thanks in advance.