Issues while using $time or $realtime inside system verilog properties

[prashanth.billava]

Hi Guys,

I am facing issues with my assertions where I am making use of $time or $realtime.

Below is the example property:

property clk_freq_check(logic [1:0] phy_rate, integer clock_period);
  real time_stamp1, time_stamp2, time_stamp;
  integer time_period; 
  @(posedge env_if.clk_in) disable iff (env_if.mac_phy_rate != phy_rate)
   $rose(env_if.pll_lock) ##20 (time_stamp1 = $time) ##1 (time_stamp2 = $time) ##1 (time_stamp = (time_stamp2 - time_stamp1)) ##1 (time_period =  $rtoi(time_stamp)) ##1 (time_period == clock_period); 
endproperty

clk_gen1_assert: assert property(clk_freq_check(2'b00, 'd8000)); 

Here is the error message:
Error-[EWSENATE] Expression with side effects
…
…, “(time_stamp1 = $time)”
Expressions with side effects not allowed in temporal expressions.
Expression: “(time_stamp1 = $time)”

And as a part of further debug, I tried to simplified the code as shown below:

property clk_freq_check(logic [1:0] phy_rate, time clock_period);
  time current_time;
  @(posedge env_if.clk_in) disable iff (env_if.mac_phy_rate != phy_rate)
   $rose(env_if.pll_lock) ##20 (current_time = $realtime) ##1 (clock_period = $realtime - current_time);
endproperty

clk_gen1_assert: assert property(clk_freq_check(2'b00, 'd8000)); 

Here is the error message:
Error-[EWSENATE] Expression with side effects
…
…, “(current_time = $realtime)”
Expressions with side effects not allowed in temporal expressions.
Expression: “(current_time = $realtime)”

In both the examples $time/$realtime was not allowed.
Could someone help with the effective solution here. Here env_if is the interface handle. I have not shown the complete module details here. Kindly assume all other things are taken care, this is mainly regarding usage of timestamps.

Thanks in advance

[ben2]

In reply to prashanth.billava:
One of the possible alternatives to write a sequence is

(sequence_expr {, sequence_match_item})[sequence_abbrev] 
// I would rewrite your code as: 
property clk_freq_check(logic [1:0] phy_rate, integer clock_period);
  realtime time_stamp1, time_stamp2, time_stamp;
  integer time_period; 
  @(posedge env_if.clk_in) disable iff (env_if.mac_phy_rate != phy_rate)
   $rose(env_if.pll_lock) |-> 
       ##20 (1, time_stamp1 = $realtime) 
       ##1  (1, time_stamp2 = $realtime) 
       ##0  (1, time_stamp = (time_stamp2 - time_stamp1))
       ##0  (1, time_period =  $rtoi(time_stamp)) //Why the ##1 in your model? 
       ##0  (time_period == clock_period); 
endproperty

// More clear 
property clk_freq_check(logic [1:0] phy_rate, integer clock_period);
  realtime time_stamp1, time_stamp2, time_stamp;
  integer time_period; 
  @(posedge env_if.clk_in) disable iff (env_if.mac_phy_rate != phy_rate)
   $rose(env_if.pll_lock) |-> 
       ##20 (1, time_stamp1 = $realtime) 
       ##1  (1, time_stamp2 = $realtime), 
                time_stamp = (time_stamp2 - time_stamp1),
                time_period =  $rtoi(time_stamp)) 
       ##0  (time_period == clock_period); 
endproperty

property clk_freq_check(logic [1:0] phy_rate, time clock_period);
  realtime current_time;
  @(posedge env_if.clk_in) disable iff (env_if.mac_phy_rate != phy_rate)
   $rose(env_if.pll_lock) |-> 
   ##20 (1, current_time = $realtime) ##1 (clock_period = $realtime - current_time);
endproperty

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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