Issue with assertions on a functionality

SystemVerilog
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1

Suppose that I have a block whose input is a 8 bit wide request bus (called req_chnls) which carry requests from 8 sources. Also there is an internal signal called ‘cursor’ which can take any value from 0 to 7. Now lets assume that out of the 8 possible requests in the ‘req_chnls’ signal, requests 7,6,3,2,1 and 0 are asserted. The functionality of the block is that, out of the asserted (active) requests it will allow ONLY one of them to pass and the one that passes is the one closest and immediately above the cursor. For instance lets assume cursor is at 5 then out of the asserted requests (viz 7,6,3,2,1,0) the one that is closest and above (6 in this example) will be selected as the output.

How can verify this functionality solely using assertions. How will those properties look line?

2

In reply to nipradee:
I suggest that you write an automatic task triggered by a fork join_none, as described in my paper

SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue

The task provides the algorithm for the verification.

Not everything needs sva!

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  • SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
  1. SVA Alternative for Complex Assertions
    Verification Horizons - March 2018 Issue | Verification Academy
  2. SVA: Package for dynamic and range delays and repeats | Verification Academy
  3. SVA in a UVM Class-based Environment
    SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
3

In reply to ben@SystemVerilog.us:

Hi Ben thanks for this input.
I was wondering if there is some restriction on the usage of task based verification methodology. I mean can this be applied when we use formal tools as well or is this meant for simulation based verification using uvm? Thanks

4

In reply to nipradee:

I believe that it is for simulation. You can use immediate assertion at the final stage to flag the final test condition.
Check with vendors.
Notesb 1) the task allows you to declare local variables, loops, case and if statements, sequences (adding @(posedge clk), SV system functions (e. G., countonesl
2) once you get that going, you may be able to convert some of that into a set of concurrent assertions. I say that because you’ll have a better understanding of the requirements. In SVA you can call functions, probably derived from your work on the task method for verification.
Ben systemverilog.us

5

In reply to ben@SystemVerilog.us:

Thanks Ben. This methodology is helpful!