IO Line delay model

SystemVerilog
, ,
1

I am trying to model a runtime random delay model for io lines. I came up with below code for introducing delay in the wire connecting the IOs.
For simplicity, I didn’t include they delay_blk code.

module top;
  
  realtime wiredly = 3;
  wire  #wiredly link;
  delay_blk#(0) d1(link);
  delay_blk#(60) d2(link);


  initial begin
     #50;
     wiredly = 5;
     #200;
     $finish;
  end

endmodule

The simulation results from VCS and Incisive are the same. I could delay the IO line “link” just by adjusting the “wiredly” variable. Can we use a variable in the delay specification of a net?

According to SV LRM, for a net, the delay element must be one of the following

delay_value ::=
unsigned_number
| real_number
| ps_identifier
| time_literal
| 1step

It doesn’t talk about any variables here(I assume unsigned_number and real_numbers are constants). Are the simulators adhering to LRM or am I missing something here?

2

In reply to [bala2910]:
ps_identifier can be a variable

3

In reply to dave_59:

In reply to [bala2910]:
ps_identifier can be a variable

Thanks a lot Dave for the quick reply.