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  • Immediate assertions vs if statement

Immediate assertions vs if statement

SystemVerilog 5107
SystemVerilog 42 Assertion system verilog 66 immediate assertion 3
Chakrakirthi
Chakrakirthi
Full Access
2 posts
February 25, 2021 at 6:46 pm

Hi,
Immediate assertions are similar to if statements, in that case why were immediate assertions created in system verilog?
Can immediate assertions use clocking reference ?

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dave_59
dave_59
Forum Moderator
8757 posts
February 26, 2021 at 8:29 am

In reply to Chakrakirthi:

An immediate assertion is much more powerful in an overall coverage metric driven closure methodology. You can easily collect coverage for any assertion passing or failing, and link that information back to a test plan to know how much your testing has covered.

Also, assertion are easy to control (i.e. turn off) from a global perspective for situations where the error can be waived.

And immediate assertion can only contain a Boolean expression. Do not confuse it with a concurrent assertion embedded in procedural code (slightly different syntax).

— Dave Rich, Verification Architect, Siemens EDA

Solution

Solution

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
2038 posts
February 26, 2021 at 8:41 am

In reply to Chakrakirthi:
The simple immediate assertion statement is a test of an expression performed when the statement is executed in the procedural code. The expression is non-temporal and is interpreted the same way as an expression in the condition of a procedural if statement. That is, if the expression evaluates to X, Z or 0, then it is interpreted as being false and the assertion fails. Otherwise, the expression is interpreted as true and the assertion passes. Typically, the conditions that cause the assertion directive to be tested are within the SystemVerilog block. The immediate assertion statements can be specified anywhere a procedural statement is allowed to be specified; this includes always, always_ff, always_comb, always_latch, initial, final. They can also be specified in functions and tasks, in modules, checkers, programs, and classes. The simple immediate assertion statement can be one of the following:
1. assert to specify that the expression holds for the design
2. assume to specify the expression is an assumption for the environment
3. cover to monitor the expression evaluation for coverage

They were created because they provide notification by the tools in the case of errors or cover, and are also used by formal verification (even without the action block).

Examples:

typedef enum {CFG_NO_JUMBO_PKTS, CFG_JUMBO_PKTS} PACKET_TYPE_e;
PACKET_TYPE_e pkt_cfg;
  always @(posedge clk) begin : aly1
    if (sop && pkt_size == 'h8000) // start_of_packet
       a_plklen : assert (pkt_cfg==CFG_NO_JUMBO_PKTS && pkt_len < 9576) else
         $error ("detected a jumbo pkt while current configuration prevents that");
// …code
  end : aly1

Ben Cohen
http://www.systemverilog.us/
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
...
1) SVA Package: Dynamic and range delays and repeats https://rb.gy/a89jlh
2) Free books: Component Design by Example https://rb.gy/9tcbhl
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
3) Papers:
- Understanding the SVA Engine,
https://verificationacademy.com/verification-horizons/july-2020-volume-16-issue-2
- SVA Alternative for Complex Assertions
https://verificationacademy.com/news/verification-horizons-march-2018-issue
- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment
Chakrakirthi
Chakrakirthi
Full Access
2 posts
March 01, 2021 at 1:20 pm

Thank you, both the answers were helpful

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