Immediate assertions

SystemVerilog
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1

The below immediate assertion and if else statement work exactly the same. I see in most of the places, assert is used for illustrating immediate assertion. Why not if else?

assert(a == b) $display(“expression evaluates to true”); else $display(“expression evaluates to false”);

if (a == b) $display(“expression evaluates to true”); 
else $display(“expression evaluates to false”);
2

In reply to Krishna9:

You are probably being interviewed by the same person.

https://verificationacademy.com/forums/systemverilog/immediate-assertions-vs-if-statement#reply-97120