Illegal Operand for constant expressions in system Verilog assertions

SystemVerilog
1

I have an assertion

$rose(antecedent)|->##(((no_of_clk_cycles%(2data_rate))==0)?(no_of_clk_cycles/(2data_rate):(no_of_clk_cycles/(2**data_rate)+1)) $rose(consequent);

Data rate is a 3bit variable and no_of_clock_cycle can also variable that I have to pass.

But I am getting a error
Illegal operand for constant expressions

Could you please suggest me how to resolve this?

2

In reply to SUBHAM RAY SINGH:
I believe that what you want is


// Simplify your expressions with the use of the "let" 
    let div=(no_of_clk_cycles%(2**data_rate); 
    bit antecedent, consequent; 
    ap_if: assert property(@(posedge clk) 
      $rose(antecedent)|->
          if(div==0) ##0 $rose(consequent) 
          else ##1 $rose(consequent)); 
// SVA does NOT have the ? : opr 
// It has 
/* property_statement ::=
     property_expr ;
   | case ( expression_or_dist ) property_case_item
   { property_case_item } endcase
   | if ( expression_or_dist ) property_expr  // <---------------
   [ else property_expr ] */

In addition, if you need dynamic repeats or delays (possibly with ranges) consider
using my SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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