If selection logic inside module is hitting unknown or bad value

SystemVerilog
1

I am finding a way to add the selection logic inside module.
Please note I am not following the exact syntax for the snippet shown below.
Some variable declarations might be missing (Assume its declared)

module test_module();

       initial begin
        if ($test$plusargs("MISALIGN_LN0_DATA")) begin
          misalign_ln0_data = 1'b1;
        end
        else begin  
          misalign_ln0_data = 1'b0;
        end
       end

       if(misalign_ln0_data) begin     
	assign ss_tb.symbol_data_ln0[9] = ....;
        assign ss_tb.symbol_data_ln0[8] = ....;
       end
       else begin   
         assign ss_tb.symbol_data_ln0[9] = ....;
         assign ss_tb.symbol_data_ln0[8] = ....;
       end  

endmodule

The issue is with the selection “if(misalign_ln0_data) begin”…
I am facing below error signature. I cannot use this inside initial block, as I have continuous statements.
Is there any other way to do it?

Error signature:
Error-[V2KGEUV] Unknown or bad value for genvar
1019 …[file path]…, 240
1020 Elaboration time unknown or bad value encountered for generate if-statement
1021 condition expression.
1022 Please make sure it is elaboration time constant.

Thanks in advance
Prashanth

2

In reply to prashanth.billava:

There is no generate block shown in your code. What is “ss_tb” and “symbol_data_ln0”?

  1. If “ss_tb” is a module and “symbol_data_ln0” is a net inside that module:
  
  assign ss_tb.symbol_data_ln0[9] = ($test$plusargs("MISALIGN_LN0_DATA")) ? (... some value ...) : (... some other value ...);
  assign ss_tb.symbol_data_ln0[8] = ($test$plusargs("MISALIGN_LN0_DATA")) ? (... some value ...) : (... some other value ...);

  // Alternative method using generate block
  genvar i;
  generate
    for(i=0;i<SYMBOL_LN0_SIZE;i++) begin
      assign ss_tb.symbol_data_ln0[i] = ($test$plusargs("MISALIGN_LN0_DATA")) ? (... some value ...) : (... some other value ...);
    end
  endgenerate
  1. If “ss_tb” is a class and “symbol_data_ln0” is a variable inside that class. Then you just need to assign the value once in the initial block.
 initial begin
   if ($test$plusargs("MISALIGN_LN0_DATA")) begin
     ss_tb.symbol_data_ln0[8] = ...; // Assuming ss_tb is not null
     ss_tb.symbol_data_ln0[9] = ...; // Assuming ss_tb is not null
   end else begin  
     ss_tb.symbol_data_ln0[8] = ...; // Assuming ss_tb is not null
     ss_tb.symbol_data_ln0[9] = ...; // Assuming ss_tb is not null
     
   end
 end

Please clarify about the entities.

3

In reply to sharvil111:

In reply to prashanth.billava:
There is no generate block shown in your code. What is “ss_tb” and “symbol_data_ln0”?

Yes there is a conditional if-generate. The generate/endgenerate keywords are optional.

The best thing to do is make misalign_ln0_data a parameter. Some tools will allow you to override a parameter from the command line.

Otherwise you will have to put a conditional branch with each assign statement.

assign ss_tb.symbol_data_ln0[9] = misalign_ln0_data ? .... : ....;
assign ss_tb.symbol_data_ln0[8] = misalign_ln0_data ? .... : ....;
4

In reply to dave_59:

As per OP’s code, “misalign_ln0_data” is assigned in procedural block. So I assumed that misalign_ln0_data is not a parameter. I agree that misalign_ln0_data should ideally be declared as parameter but that was not something that was shown in the original code (If usage of ternary is to be done then simple variable misalign_ln0_data can also suffice).

5

In reply to sharvil111:
I also assumed that was a variable that was set once at the beginning of simulation using $test$plusargs. That is the reason for the generate-if error. I was suggesting that they change it to a parameter to remove the error and set it on the command line of their tool supports it.

Otherwise they need to convert the generate block to the ternary operator ‘?:’.

6

In reply to dave_59:

Totally agree. Either use parameter or use testplusargs with ternary.