If selection logic inside module is hitting unknown or bad value

SystemVerilog
2

In reply to prashanth.billava:

There is no generate block shown in your code. What is “ss_tb” and “symbol_data_ln0”?

  1. If “ss_tb” is a module and “symbol_data_ln0” is a net inside that module:
  
  assign ss_tb.symbol_data_ln0[9] = ($test$plusargs("MISALIGN_LN0_DATA")) ? (... some value ...) : (... some other value ...);
  assign ss_tb.symbol_data_ln0[8] = ($test$plusargs("MISALIGN_LN0_DATA")) ? (... some value ...) : (... some other value ...);

  // Alternative method using generate block
  genvar i;
  generate
    for(i=0;i<SYMBOL_LN0_SIZE;i++) begin
      assign ss_tb.symbol_data_ln0[i] = ($test$plusargs("MISALIGN_LN0_DATA")) ? (... some value ...) : (... some other value ...);
    end
  endgenerate
  1. If “ss_tb” is a class and “symbol_data_ln0” is a variable inside that class. Then you just need to assign the value once in the initial block.
 initial begin
   if ($test$plusargs("MISALIGN_LN0_DATA")) begin
     ss_tb.symbol_data_ln0[8] = ...; // Assuming ss_tb is not null
     ss_tb.symbol_data_ln0[9] = ...; // Assuming ss_tb is not null
   end else begin  
     ss_tb.symbol_data_ln0[8] = ...; // Assuming ss_tb is not null
     ss_tb.symbol_data_ln0[9] = ...; // Assuming ss_tb is not null
     
   end
 end

Please clarify about the entities.