How super.new and super.data functions?

SystemVerilog
, ,
1 
class A;
  int data;
  
  function new(input int x);
    this.data = x;
  endfunction
  
endclass

class B extends A;
  function new(input int y, input int z);
    super.new(z);
    super.data = y;
    //this.data = 3;
  endfunction
  
endclass

module top;
  
  initial begin
    A a;
    B b;
    a = new(4);
    b = new(7,9);
       
    #5 $display("Data in A is %d", a.data);
    #5 $display("Data in B is %d", b.data);
  end
  
endmodule

First A constructor sets A data to be 4. Very fine.
Next super.new() in B constructor sets A data to be 9. Shouldnt it get overwritten to 9 from 4?
Now super.data = 7 should again overwrite 9 to 7. Hence a.data shouldnt it be 7? (4->9->7)
Also why is B’s data getting 7? Im calling super.data, not this.data.

2

There are two different objects. When you create object ‘a’, it creates separate memory space for ‘data’ and assigns it to value 4. Now when you create object ‘b’, it again creates new memory for ‘data’ and assigns it value ‘7’. Thereafter, it sets the value of ‘data’ to ‘9’ due to ‘super.data=y’.

Calling ‘super.data’ is same as calling ‘this.data’ since ‘data’ variable exist only in parent class.

In a nutshell, each time you call a constructor, a new memory is created. This memory/variable is independent of other objects of the class (static variables are an exception).

Hence, ‘a.data’ displays 4 which was assigned to memory of ‘data’ variable for object ‘a’ and ‘b.data’ displays 7 which was assigned to memory of ‘data’ variable for object ‘b’.

Refer to this link for more information. Also refer to Chapter-8 in detail.