How to prevent SVA from checking at first cock cycle

SystemVerilog
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Scenario:
I am checking the value of valid signal in reset state. Here reset will start from “1st” clock cycle. So when I assert assertion it is starting from “1st” clock.

Problem:
SVA Engine will sample at previous timeslot so here value of valid when first posedge occurs is “X”. But I am expecting zero, So how can I prevent SVA “not to check at 1st posedge”.

One Solution which I know: I can write some glue logic in always block and by using some variable I can disable(disable iff) it for first 2 or 3 clock cycles.

But here I am having multiple clocks so it is difficult to implement for every clock please suggest me the better way.

Thanks,
Pavan.

2

In reply to Pavan Kumar Kollipara:
Depending on which tool you use, there will be some way to use an initialisation sequence. There you could set the reset for 1 clock cycle. Property evaluation will start after the initialisation sequence.

Another option could be to use assumptions inside an “initial” block to initialize some signals.

3

In reply to katce:

See. $assertoff scope for specific immediate assertion | Verification Academy

Also do a Google search on
Verificationacademy.com assertoff cohen

I addressed this on many posts.
Ben systemverilog.us