How to find bugs in black box testing

SystemVerilog
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1

How to find bugs in black box testing (Not have access to see into the design code or flow of the design)??

2

In reply to Subbi Reddy:

In addition to the DUT you need to have a specification or model of how the DUT is expected to behave. You feed stimuli into the DUT, capture the DUT response, and check that the DUT response is consistent with the specification / model. If it isn’t consistent there could be a bug in the DUT, or in the specification / model, or in the test, or in the simulator, etc.

3

In reply to sbellock:

  1. How convertion will happen internally from one format to another format
    Ex: address A=0001 at(Little Endian) interface and at DUT side same address is A=1000(Big Endian)
  2. Please give me some more example to access data from dut to confirm verification side doesn’t went wrong?
  3. Interface is one format(Little Endian) and DUT is another format(Big Endian)
    Ex if more than 3000 addresses have, how to confirm each address gone correctly and how to confirm one address went wrong or incorrectly?

please clarify me for above Queries

4

In reply to Subbi Reddy:

One needs more information than what you have provided to know if the DUT is behaving correctly or not. For example, if you have an adder that is supposed to add (A+B) and you connect it up so that it does (B + A), that mistake will not be detectable using simple logic simulation. (there might be detectable difference in propagation delays). That is the associative property of addition. The same does not hold for subtraction or division.

If your DUT is just a simple one-port memory, then the endianness will not mater. But if your DUT is doing something like calculating the some complex equation and putting the result in a particular location, than that will be detectable.

5

In reply to dave_59:

“If your DUT is just a simple one-port memory, then the endianness will not mater. But if your DUT is doing something like calculating the some complex equation and putting the result in a particular location, than that will be detectable.”
1. Here Particular location means in Buffer??
(or)
please mention some examples for particular locations??

  2.How to find endian(little or Big endian) format bugs while reading or writing into the DUT??
   a) Any simple way to find out manipulated area(address or operation or data stored) like In large memory areas, complex design and complex operations??

please give me clarity on above Queries