How "dist" constraint works

SystemVerilog
1 
class a;
  rand enum bit {bad_pkt,good_pkt} pkt_type1;

  constraint c {
     pkt_type1 dist {good_pkt:=5,bad_pkt:=15};
  }

endclass


module tb();

  initial begin
    repeat (20) begin
      a a1 = new();
      a1.randomize();

      $display("%s",a1.pkt_type1.name());
    end
  end

endmodule

Result: no. of good_pkt = 5 and no. of bad_pkt = 15. Expected result.

But, when I write following code:

class a;
  rand enum bit {bad_pkt,good_pkt} pkt_type1;

  constraint c {
     pkt_type1 dist {good_pkt:=1,bad_pkt:=3};
  }

endclass


module tb();

  initial begin
    repeat (20) begin
      a a1 = new();
      a1.randomize();

      $display("%s",a1.pkt_type1.name());
    end
  end

endmodule

Result is no. of good_pkt = 8 and no. of bad_pkt = 12 which is not expected.

**In both the code ratio is same then why there is difference in result?
**
Thanks,
Kavish

2

In reply to shahkavish77:

Please use code tags making your code easier to read. I have added them for you.

The first case you were very lucky to hit the exact distribution. The odds of getting a perfect distribution are very low. See randomisation_dist | Verification Academy and
distributed weightage constraint | Verification Academy

Also, your code is technically illegal. See function arguments not initializing variable inside the body | Verification Academy