How can I print the class name only?

SystemVerilog
1

I would like to print the class name only. Is there a method or function? Using %m, return the full hierarchy. And get_name(), returns the name provided by the new constructor. I just want the class name provided.

2

In reply to DVCoder:

If you are using the OVM/UVM, get_type_name() returns the string used to register it with the factory.

3

In reply to dave_59:

Dave, a related question. Suppose I have a hierarchy of test classes:

class base_test extends uvm_test;
  function new(string name="base_test", uvm_component parent=null);
    super.new(name, parent);
  endfunction
endclass

class derived_test extends base_test;
  function new(string name="derived_test", uvm_component parent=null);
    super.new(name, parent);
  endfunction
endclass

and I don’t want users to run base_test, as it’s a base class which doesn’t do anything useful. If I put this code in base_test:

string  l_testname;
    $value$plusargs("UVM_TESTNAME=%s", l_testname);
    if(l_testname == XXXX)
      `uvm_fatal(my_name, "This is a base test and should not be run.")

What should I use for XXXX, to get a fatal when +UVM_TESTNAME=base_test, but not when +UVM_TESTNAME = derived_test? Yes, I can use a string literal but I have other applications for this kind of code so I’d like to be more general.

When +UVM_TESTNAME=base_test :
get_name returns uvm_test_top
get_full_name returns uvm_test_top
get_type_name returns base_test - the if is satisfied, the test will fatal (Good)

When +UVM_TESTNAME=derived_test :
get_name returns uvm_test_top
get_full_name returns uvm_test_top
get_type_name returns derived_test - the if is satisfied, the test will fatal (Bad)

I need a way to set XXXX to “base_test”, no matter which test is actually run. Again, I can do that with a string literal but is there a way to get the name of the class where the code actually lives?

One way that seems to work is to declare a local variable “my_name” in each test class, for example:

class base_test extends uvm_test;
   string my_name = "base_test";
...
class derived_test extends base_test;
   string my_name = "derived_test";
...

Then when (say) derived_test.build_phase calls super.build_phase, and base_test.build_phase contains my checking code:

$value$plusargs("UVM_TESTNAME=%s", l_testname);
    if(l_testname == my_name)
      `uvm_fatal(my_name, "This is a base test and should not be run.")

The check will fatal when +UVM_TESTNAME=base_test and will not fatal when +UVM_TESTNAME=derived_test. This only works if the derived classes declares their own local “my_name”, which they can set without disturbing the base_test variable my_name. This seems like bad OO practice, however. And it’s one more thing to have to remember.

4

In reply to scott_barvian:

The simplest solution is not registering your base_test with the factory. Then +UVM_TESTNAME=base_test will not work and you don’t have to do anything.

Otherwise the `uvm_component_util already provides a type_name variable that you can use

if (get_type_name==type_name) ...

BTW IEEE UVM 1800.2-2020 provides `uvm_component_abstract_utils which allows you to declare your base test class as virtual, so it cannot be constructed.

5

In reply to dave_59:

“Not registering with the factory” meaning not calling `uvm_component_utils. It took me a while to remember what that meant. That’s all I need for this application, the simplest solution is the best.

However, if I leave in the `uvm_component_utils, there is no type_name variable. We are back on UVM 1.1d so perhaps that variable doesn’t exist there.

6

In reply to scott_barvian:

Well if you don’t want your users to run base_test (right thing BTW), simply make that an abstract class - OOP way :-)

Cheers
Srini