In reply to scott_barvian:
The simplest solution is not registering your base_test with the factory. Then +UVM_TESTNAME=base_test will not work and you don’t have to do anything.
Otherwise the `uvm_component_util already provides a type_name variable that you can use
if (get_type_name==type_name) ...
BTW IEEE UVM 1800.2-2020 provides `uvm_component_abstract_utils which allows you to declare your base test class as virtual, so it cannot be constructed.