How to assign values to struct inside another struct

SystemVerilog
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1

Hi,

how to pass values to the struct fields inside another struct within single line?

typedef struct {
	int unsigned test1;
	int unsigned test2;
	int unsigned test3;
} type_set1;

typedef struct {
	int unsigned test4;
	int unsigned test5;
} type_set2;

typedef struct {
	type_set1    reference_type;
	type_set2 reference_content;
} type_ref_1;

typedef struct {
	int unsigned          test6;
	int unsigned          test7;
	type_ref_1  list[];
} type_info;


type_info info1 = '{1,2,'{'{3,4,5},'{6,7}}} // ASSIGNMENT 1

Does my info1 assignment is correct? If not could anyone please correct it?
Also type_ref_1 list → what will be the behavior of this statement ?

2

In reply to rr2007:

It’s not correct. Try it for yourself and see the error you get.

I don’t understand your last question. You are declaring a dynamic array.

3

In reply to dave_59:

Yes, I am using a dynamic array of specifed type.
Also if I am using a union how can I pass values to one of the union member.

Example:

typedef struct {
	int unsigned test1;
	int unsigned test2;
	int unsigned test3;
} type_set1;
 
typedef struct {
	int unsigned test4;
	int unsigned test5;
} type_set2;
 
typedef union {
	type_set1    reference_type;
	type_set2 reference_content;

} type_ref_1;
 
typedef struct {
	int unsigned          test6;
	int unsigned          test7;
	type_ref_1  list;
} type_info;
type_info info1 = '{1,2, ???

How can I pass values, since union can access one at a time and I want reference_type in my union. How can I achieve this? I tried with tagged but the tool is not supporting “union tagged”

4

In reply to rr2007:

Unpacked or untagged unions have little use in SystemVerilog. You cannot use an assignment pattern with a union; only array’s and struct’s.