How to assign associate arrays to packed arrays in SystemVerilog

SystemVerilog
,
1

Hi,

I need some help where I am getting “Illegal range in part select” :
The range of the part select is illegal:
packed_a[div_8][(8’h8*mod_8+8’b7) - 8’b1):(8’h08 * mod_8)]

I am trying the following:

bit[7:0][63:0] packed_a;
bit[7:0][15:0] data;
bit[7:0][63:0] associate_arr[logic];
logic addr;
< logic to get address>;

for (int i=0; i<16;i++) begin
 associate_arr[addr][i] =  data[i];
end
for (int i=16; i<64;i++) begin
 associate_arr[addr][i] =  8'b0;
end

foreach(associative_arr[i]) begin
  for (int j=0; j< 64; j++) begin
        mod_8 = j%8;       
        div_8 = j/8;
        packed_a[div_8][(8'h8*mod_8 +8'h7) :(8'h8*mod_8)] = associate_arr[i][j];
end

Really appreciate your help!

2

In reply to Mahak:

See Range must be bounded by constant expressions | Verification Academy

3

In reply to dave_59:

Thanks Dave!
I figured it out yesterday evening too :)