Hold a register value until a control signal is seen

SystemVerilog
, ,
1

How to hold a RDATA by an AXI SLAVE until an RREADY is seen from an AXI Master ?
My code looks like this :

if(arvalid)
begin
rid = 0;
rresp = 2’b0;
rlast = 1;
rvalid = 1;
rdata = memory_dut[i];
i = i+1;
end

Currently, my RREADY comes in the next clock cycle and by then rdata is driven to 'hX. I would like to hold rdata until RREADY is seen.

2

Do i = i+1 only if rready and rvalid is seen